Clock-Gated Dual Edge-Triggered Flip-Flop Architectures for Low-Power VLSI Systems

Abstract

As digital systems move toward ultra-low power operation and higher performance, reducing clockrelated power has become a major challenge in modern VLSI design, from the clock network alone can consume a large portion of total chip power. This work presents a Dual Edge Triggered flip-flop clock-gated architecture aimed at minimizing dynamic power dissipation while maintaining high-speed performance. Both rising and falling clock edges are captured by Dual Edge Triggered flip-flops, allowing the frequency of clock to be reduced for the same throughput, thereby lowering switching losses; however, conventional DET designs still suffer from unnecessary clock transitions during idle conditions. To overcome this limitation, a fine-grain clock gating mechanism is introduced as the primary contribution of this work, where gating logic intelligently disables clock activity when data transitions are absent, significantly reducing switching power in both the flip-flop and the clock distribution path. Six DET flip-flop architectures—SDET, TSPC-SDET, FS-TSPC-DET, STC-DET, LPLD-DET, and LPHD-DET—are designed and simulated using predictive 45nm CMOS technology, and comprehensive SPICE simulations are performed to evaluate propagation delay, average power, and area across 0.5 V to 1.0 V of voltage supply at 50 MHz. Simulated results show that integrating clock gating achieves substantial power savings compared to non-gated DET designs with minimal delay overhead. Among the evaluated designs, the proposed clock-gated LPHD-DET and LPLD-DET flip-flops provide the best performance balance between speed, area, and power optimization, making the architecture highly applicable for low-power VLSI systems such as IoT devices, wearable electronics, and batteryoperated embedded systems.