FPGA-Based Digital Signal Processing Architecture for Real-Time Communication Systems

Abstract

Real-time communication receivers require deterministic, high-throughput digital signal processing while retaining sufficient flexibility for changes in modulation, filtering, channel bandwidth, and interface standards. This methodology paper presents a streaming field-programmable gate array (FPGA) architecture that combines numerically controlled carrier generation, quadrature mixing, finite-impulse-response pulse shaping/matched filtering, frequency-domain processing, symbol decision, and buffered input/output within a fixed-point pipeline. The proposed workflow begins with floating-point algorithm validation and proceeds through word-length selection, module partitioning, register-transfer-level implementation, cycle-accurate verification, and device-oriented timing/resource estimation. A QPSK/AWGN behavioral testbench is used as a reproducible communication workload. The simulated bit-error-rate curve closely follows the theoretical QPSK/BPSK relation from 0 to 10 dB Eb/N0, while the architecture is designed for one sample per clock after pipeline fill. At a 100 MHz target clock, an analytical pipeline depth of 132 cycles corresponds to approximately 1.32 microseconds of deterministic internal latency. The methodology emphasizes pipelining, local memory, fixed-point arithmetic, and reusable IP boundaries, making it suitable for software-defined radio, OFDM front ends, telemetry links, and other real-time digital communication systems. Hardware resource figures are reported as architecture-level budgets rather than post-route measurements, preserving a clear distinction between behavioral verification and final implementation results.