Development of Microcontroller-Based Automatic Power Factor Correction Systems

Abstract

Low power factor in installations dominated by induction motors, transformers, fluorescent lighting and other inductive loads increases line current, copper loss, voltage drop and apparent-power demand. This paper presents a compact methodology for developing a microcontroller-based automatic power factor correction (APFC) system intended for low-voltage single-phase loads. The proposed system measures the phase displacement between voltage and current, calculates the instantaneous displacement power factor, and switches a binary-weighted capacitor bank through isolated relay drivers. The controller uses a dead-band strategy to prevent unnecessary switching when the measured power factor is near the target. A 230 V, 50 Hz design model is considered with 5, 10, 20 and 40 µF capacitor steps. The methodology combines sensing-circuit design, zero-cross conditioning, embedded control, capacitor sizing, protection and a calculation-backed evaluation procedure. Representative design-evaluation cases indicate that the controller can raise lagging power factor from 0.62–0.78 to approximately 0.95–0.97 while reducing line current by about 19.6–34.7% at constant real power. The proposed approach is low-cost, modular and consistent with earlier microcontroller-based compensation research published in recent years.

Low power factor in installations dominated by induction motors, transformers, fluorescent lighting and other inductive loads increases line current, copper loss, voltage drop and apparent-power demand. This paper presents a compact methodology for developing a microcontroller-based automatic power factor correction (APFC) system intended for low-voltage single-phase loads. The proposed system measures the phase displacement between voltage and current, calculates the instantaneous displacement power factor, and switches a binary-weighted capacitor bank through isolated relay drivers. The controller uses a dead-band strategy to prevent unnecessary switching when the measured power factor is near the target. A 230 V, 50 Hz design model is considered with 5, 10, 20 and 40 µF capacitor steps. The methodology combines sensing-circuit design, zero-cross conditioning, embedded control, capacitor sizing, protection and a calculation-backed evaluation procedure. Representative design-evaluation cases indicate that the controller can raise lagging power factor from 0.62–0.78 to approximately 0.95–0.97 while reducing line current by about 19.6–34.7% at constant real power. The proposed approach is low-cost, modular and consistent with earlier microcontroller-based compensation research published in recent years.