Deep Learning and Optimization Approaches in Deep Learning-Based Area Efficient 1024-Point Pipelined Radix-4 FFT Processor for Biomedical Application: A Review

Abstract

The growing demand for real-time biomedical signal processing has led to the development of high-speed and area-efficient Fast Fourier Transform (FFT) processors. Among various architectures, the 1024-point pipelined radix-4 FFT processor has emerged as a promising solution due to its reduced computational complexity, high throughput, and efficient hardware utilization. This paper presents a comprehensive review of deep learning and optimization approaches for designing area-efficient FFT processors tailored for biomedical applications such as ECG, EEG, and medical imaging. The radix-4 FFT algorithm reduces arithmetic operations compared to radix-2 while maintaining computational complexity of , significantly improving processing efficiency. Pipelined architectures, particularly Single-path Delay Feedback (SDF), enhance throughput and memory efficiency, making them suitable for real-time applications. Recent studies highlight the integration of deep learning techniques for adaptive optimization of hardware parameters, including pipeline stages, memory allocation, and arithmetic precision. Additionally, approximate computing and parallel architectures have been explored to reduce power consumption and chip area. This review systematically analyses recent advancements (2020–2023), compares different design methodologies, and identifies challenges such as scalability, energy efficiency, and real-time deployment. The findings indicate that hybrid approaches combining deep learning and hardware optimization offer significant improvements in performance and efficiency.