FPGA Implementation of Real-Time Traffic Monitoring and Intelligent Signal Control System

Abstract

Urban intersections controlled by fixed-cycle traffic lights cannot react efficiently to rapid variations in vehicle demand. This paper presents a methodology for an FPGA-based real-time traffic monitoring and intelligent signal control system that combines lane-level sensing, density estimation, adaptive green-time computation, and a safety-constrained finite-state machine. Vehicle presence is represented by IR or camera-derived digital occupancy signals sampled at one-second intervals. The controller estimates approach queues, assigns bounded green times, handles pedestrian or emergency priority requests, and drives red-yellow-green outputs through deterministic hardware logic. The proposed design is specified in synthesizable Verilog/VHDL so that the monitoring and control paths execute concurrently with predictable latency. A reproducible 30-minute queueing simulation was used to compare the proposed adaptive policy with a fixed 45-second green baseline under four traffic patterns. The modeled results reduced average waiting time by approximately 29.8% across the scenarios, with the largest benefit under directional imbalance. These results are simulation-based rather than field measurements and are intended to demonstrate the evaluation procedure that should accompany RTL simulation, synthesis, timing analysis, and hardware-in-the-loop testing. The methodology therefore provides a compact pathway from traffic sensing to FPGA deployment for low-latency intelligent intersections