Design and Implementation of FPGA-Based Real-Time Digital Signal Processing Architecture

Abstract

Field-programmable gate arrays (FPGAs) provide a suitable platform for real-time digital signal processing (DSP) because their configurable logic, embedded multipliers, block memories, and deterministic pipelines allow signal-processing tasks to be executed with high concurrency. This paper presents a methodology for the design and implementation of a streaming FPGA-based real-time DSP architecture that combines input buffering, a fixed-point finite impulse response (FIR) filter, frame formation, windowing, a fast Fourier transform (FFT) stage, and output generation. The architecture is organized as independent pipeline modules connected by synchronous streaming interfaces so that one sample can be accepted every clock cycle after pipeline fill. A 16-bit Q1.15 numerical format, a 32-tap low-pass FIR stage, and a 256-point FFT are used as a representative configuration. Functional verification was performed using a software model that reproduces the fixed-point quantization behavior of the proposed FIR datapath. For a 1 MHz sampled test signal containing a 50 kHz desired component and a 220 kHz interferer, the fixed-point model showed a root-mean-square deviation of 0.000134 relative to the floating-point reference and an equivalent numerical SNR of 70.69 dB. The post-filter spectrum reduced the interferer by approximately 70.16 dB relative to the desired component. The methodology emphasizes pipelining, deterministic latency, resource-aware arithmetic, modular verification, and synthesis-ready interfaces. The study demonstrates how an FPGA DSP datapath can be structured for communications, instrumentation, audio, biomedical, and embedded real-time applications while maintaining a clear path from algorithm specification to hardware verification.