Comparative Analysis of FPGA-Based High-Speed Image Processing Architectures for Real-Time Applications

Abstract

Field-programmable gate arrays (FPGAs) are widely used in real-time image processing because they combine fine-grained parallelism, deterministic latency, reconfigurability, and comparatively low power consumption. However, published FPGA image-processing systems employ different architectural styles, devices, image resolutions, algorithms, and performance metrics, making direct comparison difficult. This methodology paper develops a structured framework for comparing high-speed FPGA architectures used in real-time applications. The study classifies representative designs into systolic/window-based arrays, deeply pipelined streaming architectures, high-level-synthesis (HLS)-optimized datapaths, programmable soft-core/many-core architectures, and heterogeneous FPGA–processor systems. Literature published up to 2021 is evaluated using throughput, latency, logic and memory utilization, power/energy behavior, flexibility, scalability, and development complexity. The proposed method normalizes results at the architectural level rather than claiming device-independent numerical equivalence across different FPGA generations. Evidence from SIFT, Harris, Canny, AKAZE, HOG, and generic window-processing implementations shows that deeply pipelined streaming designs provide the highest deterministic throughput when the algorithm is stable, while HLS and processor-based approaches offer stronger design productivity and reprogrammability. Heterogeneous SoC solutions provide an effective compromise for algorithms combining control-intensive and data-parallel stages. The analysis indicates that architecture selection for real-time imaging should be treated as a multi-objective decision involving speed, resource efficiency, flexibility, and implementation effort rather than throughput alone.