DESIGN & COMPARISON OF NOVEL LOW POWER, SUB THRESHOLD SCHMITT TRIGGER BASED SRAM & SOURCE COUPLED LOGIC FOR COGNITIVE APPLICATIONS

Abstract

The wide utilization & acceptance of low power devices leads to drastic growth in the miniaturization of electronic.
The performance of these low power devices on par with the efficiency, But the limitations of the devices are only power and
delay, as the devices are operating under the sub threshold operations. SRAM is one of the major component in digital design,
occupies 50% in area and consumes nearly 40% of power. In this paper a novel sub threshold SRAM designs have proposed
to improve the stability in read & write operations along with power and delay. The main focus of this research work is to
address the leakage power, when the circuits are operating under the sub threshold region. The critical limitation in this
design is the leakage power as the technology is increasing. As the technology increasing at a rapid rate the leakage power is
dominating the dynamic power. This amount of power need to be controlled at all the levels of abstractions in the entire
design. Another issue is with the delay, where this leads to reduce the speed of operation. This research work describes the
two novel proposed designs which may be helpful to implement SRAM, to satisfy the above requirement. i.e. Sub threshold
Schmitt trigger based SRAM & source coupled logic based SRAM. The first part of the paper describes the design and
implementation of sub threshold Schmitt trigger based SRAM and analyzing the performance by write & read operations,
performance through power and delay. In the second part, analysis of source coupled logic functionally and performance is
analyzed and estimated, finally made a comparison between these two novel designs in power and delay under sub threshold
operation. Conclusion is made based on the experimental results obtained for high frequency, low power electronics