A SYSTEMATIC STUDY ON ARCHITECTURAL LEVEL ESTIMATION AND SYNTHESIS

Abstract

The study of Architecture level estimation and synthesis aspires to obtain more accurate results at architectural
level. In modern process power dissipation issues are increasingly significant. Most exciting power analyses tools aim to
have high accuracy by reckoning estimation of power designing. This paper represents framework of power dissipation
in IIR filters and different sub architectural levels which are salient for lowering power consumption. The static power
ratio at 0.48 in bit-serial filter has been given for FIR filter whereas 0.36 for the bit-serial filter has been given for IIRFilter