FFT IMPLEMENTATION BY FPGA USING VEDIC MATHEMATICS

Abstract

Fast Fourier Transform is important data processing technique in communication systems and DSP systems. In this, we propose high speed and area efficient 8 point FFT processor using Vedic algorithm. For the reduction of computational complexity and area, we develop FFT architecture by designing a radix-4 algorithm and optimizing the realization by Vedic algorithm. Moreover, the design achieves very high speed, which makes them suitable for the most demanding applications of FFT. The proposed radix-4 Vedic algorithm based architecture requires lesser hardware resources. The synthesis results are same as that of theoretical analysis and it is observed that more than 15% reduction can be achieved in terms of slices count. In addition, the dynamic power consumption can be reduced and speed can be increased by as much as 16% using Vedic algorithm.