Recent Advances in Hardware Efficiency of CNN Architecture Design Using Decoder-Based Low Power Approximate Multiplier and Error Reduced Carry Prediction Approximate Adder for MNIST Dataset Classification: A Systematic Review

Abstract

The rapid growth of deep learning applications, particularly Convolutional Neural Networks (CNNs), has significantly increased the demand for efficient hardware architectures capable of delivering high performance with minimal power and area consumption. CNN-based systems are widely used in applications such as image classification, pattern recognition, and biomedical signal analysis. However, their computational complexity, especially due to multiply–accumulate (MAC) operations, poses challenges for energy-efficient hardware implementation. Approximate computing has emerged as a promising solution to address these challenges by trading off computational accuracy for improved power efficiency and reduced hardware complexity. In particular, decoder-based low power approximate multipliers and error-reduced carry prediction approximate adders have gained attention for optimizing CNN hardware accelerators. These techniques exploit the inherent error resilience of neural networks, allowing significant reductions in energy consumption while maintaining acceptable classification accuracy. Recent studies demonstrate that approximate multipliers can reduce energy consumption by up to 80% in CNN operations without significant degradation in performance. Additionally, approximate arithmetic units enable efficient hardware acceleration for deep learning models such as MNIST classification, where slight inaccuracies do not significantly affect output accuracy. This paper presents a systematic review of recent advances in hardware-efficient CNN architectures using approximate arithmetic techniques, highlighting trends, design methodologies, and future research challenges.