Aarthi, G. S., and E. P. Kannan. “Clock-Gated Dual Edge-Triggered Flip-Flop Architectures for Low-Power VLSI Systems”. International Journal on Advanced Computer Engineering and Communication Technology, vol. 15, no. 2, July 2026, pp. 169-76, doi:10.65521/ijacect.v15i2.3703.