Aarthi, G. S. and Kannan, E. P. (2026) “Clock-Gated Dual Edge-Triggered Flip-Flop Architectures for Low-Power VLSI Systems”, International Journal on Advanced Computer Engineering and Communication Technology, 15(2), pp. 169–176. Available at: https://journals.mriindia.com/index.php/ijacect/article/view/3703 (Accessed: 17 July 2026).