AARTHI, G. S.; KANNAN, E. P. Clock-Gated Dual Edge-Triggered Flip-Flop Architectures for Low-Power VLSI Systems. International Journal on Advanced Computer Engineering and Communication Technology, [S. l.], v. 15, n. 2, p. 169–176, 2026. Disponível em: https://journals.mriindia.com/index.php/ijacect/article/view/3703. Acesso em: 17 jul. 2026.